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PE4141
Product Specification
Figure 3. Pin Configuration (Top View)
Table 2. Pin Descriptions
Electrostatic Discharge (ESD) Precautions
This MOSFET device has minimally protected
inputs and is highly susceptible to ESD damage.
When handling this UltraCMOS? device, observe
the same precautions that you would use with
other ESD-sensitive devices.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS?
devices are immune to latch-up.
Device Description
The performance level of this MOSFET array is
Pin No.
1
2
3
4
5
6
7
8
Pin Name
IF1
GND
RF1
RF2
LO2
LO1
GND
IF2
Description
IF Output Connection (Drain)
Ground
RF Input Connection (Source)
RF Input Connection (Source)
LO Input Connection (Gate)
LO Input Connection (Gate)
Ground
IF Output Connection (Drain)
made possible by the very high linearity afforded
by Peregrine’s UltraCMOS? process. The 8-lead
MSOP package is suitable for highly magnetic
applications including Magnetic Resonance
Imaging (MRI.)
The PE4141 is an ideal MOSFET array core for a
wide range of MOSFET array products, including
module level solutions that incorporate baluns or
other single-ended matching structures enabling
Table 3. Absolute Maximum Ratings
three-port operation.
Symbol
Parameters/
Min
Max
Units
Conditions
Marking
T ST
T OP
Storage temperature
range
Operating temperature
range
-65
0
150
70
°C
°C
Packaged devices are marked with part number
“4141”, date code and lot code.
Maximum DC plus peak
V DC + AC
AC voltage across Drain-
±3.3
V
Source
Maximum DC plus peak
V DC+AC
AC voltage across Gate-
±4.2
V
Drain or Gate-Source
V ESD
ESD Sensitive Device
100
V
Exceeding absolute maximum ratings may cause
permanent damage. Operation should be
restricted to the limits in the Operating Ranges
table. Operation between operating range
maximum and absolute maximum for extended
periods may reduce reliability.
?2010-11 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0268-04 │ UltraCMOS? RFIC Solutions
Page 2 of 5
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
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